The present invention relates in general to semiconductor technology, and more particularly to structures and methods for forming shielded gate trench FETs having multiple channels along each trench sidewall.
Shielded gate trench field effect transistors (FETs) are advantageous over conventional FETs in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor without sacrificing the transistor on-resistance. FIG. 1 is a simplified cross-sectional view of a conventional shielded gate trench MOSFET 100. N-type epitaxial layer 102 extends over highly doped n-type substrate 101. Substrate 101 serves as the drain contact region. Highly doped n-type source regions 108 and highly doped p-type heavy body regions 106 are formed in p-type well region 104 which is in turn formed in epitaxial layer 102. Trench 110 extends through well region 104 and terminates in the portion of epitaxial layer 102 bounded by well region 104 and substrate 101, which is commonly referred to as the drift region.
Trench 110 includes shield electrode 114 below gate electrode 122. Gate electrode 122 is insulated from well region 104 by gate dielectric 120. Shield electrode 114 is insulated from the drift region by shield dielectric 115. Gate and shield electrodes 122,114 are insulated from each other by inter-electrode dielectric (IED) layer 116. IED layer 116 must be of sufficient quality and thickness to support the difference in potential that may exist between shield electrode 114 and gate electrode 122 during operation. Dielectric cap 124 overlays gate electrode 122 and serves to insulate gate electrode 122 from topside interconnect layer 126. Topside interconnect layer 126 extends over the structure and makes electrical contact with heavy body regions 106 and source regions 108.
While inclusion of shield electrode 114 under gate electrode 122 has improved certain performance characteristics of the transistor (such as the breakdown voltage and Cgd), further improvements in these and other electrical and structural characteristics (such as the transistor on-resistance Rdson and unclamped inductive switching UIS characteristic) have been difficult to achieve. This is because, most known techniques for improving certain electrical characteristics of the FET often adversely impact other electrical characteristics or require significant changes to the process technology.
Thus, there is a need for cost effective techniques where various electrical characteristics of a trench gate FET can be improved without compromising other electrical characteristics.